Chapter 7: Circuit Designs and Sequential Circuits

In this chapter, we introduce the most commonly used building blocks: multiplexer, decoder, and encoder. The outputs of these combinational logic circuits depend on current input values, hiding the unnecessary gate-level details to emphasize the function of the building block. This chapter also introduces sequential logic circuits, which outputs depend on both current and prior values.

Objectives

By the end of this chapter you should be able to:

• Demonstrate knowledge of multiplexer, decoder, and encoder
• Simplify the Boolean equation with k-map
• Design combinational logic circuits with logic gates
• Differentiate combinational logic circuits and sequential logic circuits
• Recall basic knowledge of SR latch: set, reset, memory and invalid state
• Evaluate internal circuit operations of D latch and D flip-flop

7.1 Combinational Circuit Design

Multiplexer

A multiplexer (or Mux), also known as a data selector, is a device that selects one among N analog or digital inputs and forwards the selected input to a single output line. If the mux has N inputs, it needs control inputs. For example, if the mux has the two inputs, it needs a ( = 1) control input. The following figure shows 2-to-1 multiplexer which has two inputs (D₀ and D₁), one output (Y), and a control input (S).

Fig. ‑. 2-to-1 Multiplexer

If the control input S is 0, the input D₀ is forwarded to the output Y. If the control input S is 1, the input D₁ is forwarded to the output Y. The following table describes the 2-to-1 multiplexer.

Table ‑. Truth Table of 2-to-1 Multiplexer

From the above table, we can notice that the value of the output Y is determined by two inputs, D₁ and D₀, and the control input S. Let’s draw K-map to simplify the Boolean equation in terms of the output Y, as shown in Fig. 7-2.

Fig. ‑. 2-to-1 Multiplexer

The simplified equation is which allows us to design logic gates for 2-to-1 multiplexer. For the multiplexer design, there needs two AND gates and one OR gate in the block of Fig. 7-1.

Fig. ‑. 2-to-1 Multiplexer

As shown in Fig. 7-3, AND₁ gate has two inputs, D₁ and S, whereas AND₂ gate has two inputs, D₀ and . The two outputs of the AND gates are fed into the OR gate which produces the output Y.

Decoder

The decoder translates the binary value into a decimal value. Fig. 7-4 shows a block diagram of 2-bit binary decoder. The 2-to-4 decoder has two inputs A₁ and A₀, and four outputs Y₃, Y₂, Y₁ and Y₀. Depending on the binary inputs A₁ and A₀, only one output will be TRUE and the other outputs will be FALSE. For example, if the binary inputs A₁A₀ is equal to ‘11’, only one output Y₃ is TRUE and the other outputs Y₂ Y₁ Y₀ are all FALSE.

Fig. ‑. Block Diagram of 2-bit Binary Decoder

The following table shows the truth table of the decoder.

Table ‑. Truth Table of 2-bit Binary Decoder

The truth table of 2-to-4 binary decoder can be mapped to K-map and we can describe the output variables in terms of input variables.

Fig. ‑. K-Map Representation of 2-bit Binary Decoder

Each output value was expressed with input variables, as shown in the above figure. We can fill the box of Fig. 7-4 with a combinational circuit of 2-bit binary decoder in the following figure:

Fig. ‑. Combinational Circuit of 2-bit Binary Decoder

The 2-to-4 binary decoder has two inputs (A₁, A₀) and four outputs (Y₃, Y₂, Y₁, and Y₀). There are four AND gates and two NOT logic gates in the block.

• AND₃ gate produces the output Y₃ with two inputs, and .
• AND₂ gate produces the output Y₂ with two inputs, and .
• AND₁ gate produces the output Y₁ with two inputs, and .
• AND₀ gate produces the output Y₀ with two inputs, and .

Encoder

The encoder is the inverse operation of a decoder. The operation is like the keyboard. Only one input is TURE (press only one button) and the others are FALSE. It generates the binary code corresponding to the input value. A 4-to-2 encoder has four inputs D₃ D₂ D₁ D₀ and two binary outputs B₁ B₀, as shown in Fig. 7-7. Only one input is TRUE and the other inputs are FALSE. For example, if the input D₃ is TRUE and the others are FALSE, it generates the corresponding binary code B₁ B₀ = 11.

Fig. ‑. 4-to-2 Encoder

The following table describe the operation of the 4-to-2 encoder.

Table ‑. Truth Table of 4-to-2 Encoder

From the above table, we can notice that the outputs B₁ and B₀ are determined by four inputs, D₃, D₂, D₁ and D₀, respectively. Using the truth table of the encoder, we can create K-map which can simplify the Boolean equation for the encoder.

To simplify the Boolean equation of the output B₁, we have the following Boolean values:

• If the inputs D₃ D₂ D₁ D₀ are equal to ‘0 0 0 1’, the output B₁ = 0
• If the inputs D₃ D₂ D₁ D₀ are equal to ‘0 0 1 0’, the output B₁ = 0
• If the inputs D₃ D₂ D₁ D₀ are equal to ‘0 1 0 0’, the output B₁ = 1
• If the inputs D₃ D₂ D₁ D₀ are equal to ‘1 0 0 0’, the output B₁ = 1

To simplify the Boolean equation of the output B₀, we have the following Boolean values:

• If the inputs D₃ D₂ D₁ D₀ are equal to ‘0 0 0 1’, the output B₀ = 0
• If the inputs D₃ D₂ D₁ D₀ are equal to ‘0 0 1 0’, the output B₀ = 1
• If the inputs D₃ D₂ D₁ D₀ are equal to ‘0 1 0 0’, the output B₀ = 0
• If the inputs D₃ D₂ D₁ D₀ are equal to ‘1 0 0 0’, the output B₀ = 1

The following figure shows the K-map representation of 4-to-2 encoder.

Fig. ‑. K-map Representation of 4-to-2 Encoder with Empty Cells

The empty cells will be filled out with X (don’t care) notation, because we don’t care the outputs B₁ and B₀ (either 0 or 1) when the other input combinations of D₃ D₂ D₁ D₀ are fed into the encoder. It seems like the case when you pressed more than two buttons simultaneously.

The K-map simplifies the Boolean equation of B₁ and B₀, as shown in Fig. 7-9. We can get the simplified equation as follows:

• B₁ = D₃ + D₂
• B₀ = D₃ + D₁

Fig. ‑. K-map Representation of 4-to-2 Encoder with X (don’t care) Notation

Let’s design logic gates for the encoder using the above figure:

Fig. ‑. Designed Encoder with logic gates

4-to-2 encoder has four inputs, i.e. D₃, D₂, D₁, D₀, and two outputs (binary code), i.e. B₁ and B₀. There are two OR gates in the block.

• OR₁ gate has two inputs, D₂ and D₃, and produces the output B₁.
• OR₀ gate has two inputs, D₁ and D₀, and produces the output B₀.

7.2 Sequential Circuits

So far, we take a look at the combinational circuit, in which the output is independent of time and only relies on the current input at that particular instant. On the other hand, the sequential circuit is the type of circuit where output not only relies on the current input but also depends on the previous output. The sequential circuit consists of a combinational circuit and storage elements. The previous input/output values are stored in storage elements.

Fig. ‑. Sequential Circuit

As shown in the above figure, the inputs directly are fed into the combinational circuit block. The combinational circuit produces outputs with current and prior input values. Some states of the combinational circuit are stored in memory elements, e.g. Flip-flops, which will be used as the prior input values. Storage elements maintain a binary state indefinitely as long as power is delivered to the circuit. There are two types of the storage elements: 1) Latch – operated with signal levels, and 2) Flip-Flop – controlled by a clock transition.

SR Latch

SR latch is the most fundamental building block using static gates, where S and R stand for set and reset. SR latch can be designed with two NOR gates. The inputs S and R are fed into each NOR gate, and the output of one NOR gate recursively is fed into the input of the other NOR gate, as shown below:

Fig. ‑. SR Latch

The outputs and represent the value of the stored state and its complement, respectively. In SR latch, there are four possible input cases:

• Case 1: S = 1, R = 0

Let’s look at the case when the inputs S = 1 and R = 0. The ‘1’ bit is the dominant input of the NOR gate. Since one of the inputs, S = 1, is TRUE, the NOR gate (N₂) produces the output FALSE which is fed into one of the inputs in the other NOR gate (N₁). Both two inputs of the NOR gate N₁ are FALSE and the NOR gate N₁ produces the output TRUE.

Fig. ‑. SR Latch When the inputs S = 1 and R = 0

• Case 2: S = 0, R = 1

Let’s look at the case when the inputs S = 0 and R = 1. The ‘1’ bit is the dominant input of the NOR gate. Since one of the inputs, R = 1, is TRUE, the NOR gate (N₁) produces the output FALSE which is fed into one of the inputs in the other NOR gate (N₂). Both two inputs of the NOR gate N₂ are FALSE and the NOR gate N₂ produces the output TRUE.

Fig. ‑. SR Latch When the inputs S = 0 and R = 1

• Case 3: S = 0, R = 0

Let’s look at the case when both inputs S and R are FALSE. Since both of inputs are FALSE, we need to consider the case whether the previous output is FALSE or TRUE. In the former case when the previous output is FALSE, both inputs of the NOR gate N₂ are FALSE and the gate produces the output TRUE. Both inputs of the other NOR gate N₁ has TRUE and FALSE, the gate produces the output FALSE. In the latter case when the previous output is TRUE, both inputs of the NOR gate N₁ are FALSE and the gate produces the output TRUE. Both inputs of the other NOR gate N₂ has TRUE and FALSE, the gate produces the output FALSE.

Fig. ‑. SR Latch When the inputs S = 0 and R = 0

In summary, if the inputs S = 0, R = 0, and , then the output . If the inputs S = 0, R = 0, and , then the output . In this case, the latch memorizes the previous state.

• Case 4: S = 1, R = 1

Let’s look at the case when both inputs S and R are TRUE. Both NOR gates have a dominant input ‘1’ and both outputs and are equal to 0. This is an invalid state. The values of and should be different. We should avoid this state.

Fig. ‑. SR Latch When the inputs S = 1 and R = 1

SR latch stores one bit of state (). The following figure shows the SR latch symbol.

Fig. ‑. SR Latch Symbol

D Latch

SR latch has an invalid state. We must do something to avoid the invalid state. D latch allows us to avoid this invalid state, where the D latch has two inputs CLK and D. The CLK input controls when the output changes, and the data input D controls what the output changes to. The function of D latch is as follows:

• When CLK = 1, D passes through to : called it a state of “transparent”
• When CLK = 0, holds its previous value: called it a state of “opaque”

Fig. ‑. D Latch, (a) Internal circuit and (b) Symbol

As shown in the above figure, D Latch Internal Circuit consists of NOT gate, two AND gates, and SR latch. There are two inputs, CLK and D, and two outputs and . The inputs, CLK and , are fed into one AND gate, and the gate produces the internal value R. On the other hand, the inputs, CLK and D, are fed into the other AND gate, and the gate produces the internal value S. The following table summarizes the internal states of the D latch.

Table ‑. Internal States of D Latch

• If CLK = 0, both of AND gates produce “0”. That means two internal inputs S and R are “0”. The latch produces and , meaning that the current output is equal to .
• If CLK = 1 and D = 0, the internal input S has a value of “0” and the internal input R has a value of “1”. The latch produces and .
• If CLK = 1 and D = 1, the internal input S has a value of “1” and the internal input R has a value of “0”. The latch produces and .

The way to respond to the clock signal is slightly different in Latch and Flip-Flop. The latch updates its state when the clock level is positive, as shown in the following figure:

Fig. ‑. Latch Respond to Positive Level

On the other hand, the flip-flop updates its state when the clock level is in a transitional state, i.e. edge triggered, as shown in the following figure:

Fig. ‑. Flip-Flop Respond to Positive or negative-edge in the Clock Cycle

That means that the flip-flop changes the state when the clock level is changed from low to high, referred to as a positive-edge response, or from high to low, referred to as a negative-edge response.

D Flip-Flop

The D flip-flop is created by connecting two gated D latches serially, and inverting the CLK input to one of them. There are two inputs, CLK and D, and it produces the output values and . The following figure shows the symbols of D flip-flop.

Fig. ‑. D Flip-Flop Symbols

In D flip-flop, D (data) passes through to when CLK rises from 0 to 1 (or from 1 to 0); otherwise, holds its previous value. value changes only on rising edge of CLK (from 0 to 1), called edge-triggered, which was represented in the inverted triangle of the above figure.

The internal circuit of D Flip-flop composes of two latches (L₁: Master, and L₂: Slave) and NOT gate, as shown in the following figure:

Fig. ‑. D Flip-Flop Internal Circuit – Master Enabled

CLK value is directly fed into L₂, but connected to L₁ after flipping CLK with NOT gate. The input D is directly fed into L₁. The output of L₁ is directly connected to the internal input N₁ of L₂. When the CLK value is zero, L₁ Latch is enabled (transparent) and the input D value can pass through L₁. On the other hand, L₂ Latch is disabled (opaque) and the internal input N₁ cannot pass through L₂.

Fig. ‑. D Flip-Flop Internal Circuit – Slave Enabled

When the CLK value is one, L₂ Latch (Slave) is enabled (transparent) and the internal input N₁ can pass through L₂. On the other hand, L₁ Latch (Master) is disabled (opaque) and the input D cannot pass through L₁, as shown in the above figure.

Thus, when the CLK value rises from 0 to 1 (on the edge of the clock), the D value passes through value.

Since D flip-flop keeps one-bit information, we can design a 4-bit register with four D flip-flops, as follows:

Fig. ‑. 4-bit Register

• D Flip-Flop₀ has the input D₀ and the output Q₀.
• D Flip-Flop₁ has the input D₁ and the output Q₁.
• D Flip-Flop₂ has the input D₂ and the output Q₂.
• D Flip-Flop₃ has the input D₃ and the output Q₃.

Notice that each edge clock CLK of D Flip-Flop is connected to the common CLK individually.