Chapter 8: Basic CPU Organization
In this chapter, we introduce the basic CPU organization and instructions. This module also shows how a CPU is made, what’s inside a CPU, how computer memory works, and how a CPU works.
Objectives
By the end of this chapter you should be able to:
- Recognize the history of Intel microprocessors
- Recall how a CPU is made from sand to chip
- List what’s inside a CPU
- Demonstrate knowledge of computer memory integrating with a CPU
8.1 Hardware Overview
Typical personal computer systems consist of lots of input/output devices, storage devices and communication interface. The input device includes keyboard, mouse. The output device includes monitor, printer, and speaker. Storage devices include CD-R/RW, DVD, and Hard disk. When you open a desktop computer case, you can see lots of electronic components in the main board. The key components of your main board are CPU and Memory.
History of Intel Processors
The early computers that used vacuum tubes were huge. The ENIAC occupied a whole room. Vacuum also took a long time to warm up and they produce a lot of excess heat and then came transistors. The transistor was invented at Bell Laboratories on December 23, 1947. The following show the history of intel processors:
Year | Processors | # of Transistors | Clock rate | Memory | Feature size |
1971 | Intel 4004 | 2,300 | 740 KHz | Up to 4,096 bytes | 10 microns |
1972 | Intel 8008 | 3,500 | 0.2 to 0.8 MHz | Up to 16 kB | 10 microns |
1964 | Intel 8080 | 4,500 | 2 MHz | Up to 64 kB | 6 microns |
1978 | Intel 8086 | 29,000 | 5 to 10 MHz | Up to 1 MB | 3 microns |
1979 | Intel 8088 | 29,000 | 5 to 10 MHz | Up to 1 MB | 3 microns |
1982 | Intel 80186 | 55,000 | 6 to 25 MHz | Up to 1 MB | 3 microns |
1982 | Intel 80286 | 134,000 | 6 to 25 MHz | Up to 16 MB | 1.5 microns |
1985 | Intel 80386 | 275,000 | 12 to 40 MHz | Up to 4 GB | 1.5 microns |
1989 | Intel 80486 | 1,180,235 | 16 to 150 MHz | Up to 4 GB Cache – 8 to 16 kB | 1 micron |
1993 | Intel Pentium 80501 | 3.1 to 3.3 million | 60 to 66 MHz | Up to 4 GB Cache – 8 kB instruction cache, 8 kB cache | 0.35 to 0.8 microns |
1995 | Intel Pentium Pro | 5.5 million | 150 – 200 MHz | Up to 64 GB L1 Cache – 8 kB instruction cache & 8 kB data cache LS Cache – 512 kB | 0.35 to 0.5 microns |
1997 | Intel Pentium II | 7.5 million | 233, 266 or 300 MHz | Up to 64 GM L1 Cache – 32 kB L2 Cache – 512 kB | 0.35 microns |
1999 | Intel Pentium II (Dixon) | 27.4 million | 400 MHz | Up to 64 GB L1 Cache – 32 kB L2 Cache – 256 kB | 180 nm |
1999 | Intel Pentium 3 Katmai | 9.5 million | 450 to 600 MHz | L1 Cache – 16 kB instruction cache & 16 kB data cache L2 Cache – 512 kB (50% of CPU speed) | 250 nm |
2001 | Intel Pentium 3 Tualatin | 45 million | 1000 to 1400 MHz | L1 Cache – 16 kB instruction cache 7 16 kB data cache L2 Cache – 256 kB or 512 kB (full speed) | 130 nm |
2000 | Intel Pentium 4 Willamette | 42 million | 1300 to 2000 MHz | L1 Cache – 20 kB L2 Cache – 256 kB | 180 nm |
2002 | Intel Pentium 4 Northwood | 55 million | 1600 to 2800 MH | L2 Cache – 512 kB | 130 nm |
2004 | Intel Pentium 4 Prescott | 112 million | 2400 to 3067 MHz | L2 Cache – 1024 kB | 90 nm |
2005 | Intel Pentium 4 Prescott 2M | 169 million | 2.8 to 4.00 GHz | L2 Cache – 2 MB | 90 nm |
2006 | Intel Pentium 4 Cedar Mill | 184 million | 3 to 3.6 GHz | L2 Cache – 2 MB | 65 nm |
The list of Intel microprocessors can be found on Wikipedia.
How A CPU Is Made
Your CPU made with sand (silicon), UV light, fire (high temperature), and water (cleaning). Intel released all the major steps in a process that normally takes hundreds of stages to complete. See how a CPU is made.
8.2 CPU Organization
What’s inside a CPU
Inside every computer is a central processing unit and inside every CPU are small components that carry out all the instructions for every program you run. These components include AND gates, OR gates, NOT gates, Clock, Multiplexer, ALU (arithmetic logic unit), etc. Data bus performs data transfer within a CPU and a computer. As shown in Fig. 8-1, CPU is organized with Program Counter (PC), Instruction Register (IR), Instruction Decoder, Control Unit, Arithmetic Logic Unit (ALU), Registers, and Buses. PC holds the address of the next instruction to be fetched from Memory. IR holds each instruction after it is fetched from Memory. Instruction Decoder decodes and interprets the contents of the IR, and splits a whole instruction into fields for the Control Unit to interpret. Control Unit co-ordinates all activities within the CPU, has connections to all parts of the CPU, and includes a sophisticated timing circuit. ALU carries out arithmetic and logical operations, exemplified with addition, comparison, Boolean AND/OR/NOT operations. Within ALU, input registers hold the input operands and output register holds the result of an ALU operation. Once completing ALU operation, the result is copied from the ALU output register to its final destination.
Fig. ‑. CPU Organization
General-purpose registers are available for the programmer to use in their programs within CPU. Typically, the programmer tries to maximize the use of these registers in order to speed program execution. Busses serve as communication highways for passing information in the computer.
The computer has memory which memorize data in a similar way we remember the past events. The register is the fastest memory which is located within CPU of the computer.
Fig. ‑. CPU Overview
The above figure shows CPU overview which consists of PC, instruction memory, registers, ALU, and Data memory. PC always holds the address of the next instruction to be fetched from Memory. Instruction, e.g. add $t1, $t2, $t3, is fetched into instruction memory. Register operands are used by an instruction in registers, where $t1 is the first source operand, $t2 is the second source operand, and $t3 is the storage of the result. ALU executes an arithmetic operation, e.g. Sum of $t1 and $t2. The result from the ALU or memory is written back into the register file ($t3). In the figure, ALU results and the output of data memory can’t just join wires together. The red dash-dot line can be designed with the multiplexer to put the wires together.
The following figure shows CPU control with multiplexers. The first multiplexer controls what value replaces the PC (PC + 4 or the branch destination address), where the Mux is controlled by the AND gate with the Zero output of ALU and a control signal. The second multiplexer steers the output of the ALU or the output of the data memory. The third one determines whether the second ALU input is from the registers or from the offset field of the instruction (for a load or store).
Fig. ‑. CPU Control with Multiplexer