Chapter 2: Overview on Computing Hardware

In this chapter, we explore basic logic gates that take one or more binary inputs and produce a binary output. In addition, we cover how CMOS transistors are used to implement logic gates.

Objectives

By the end of this chapter you should be able to:

• Explain the basic logic gates and logic levels.
• Explain what noise is and what noise margin is.
• Understand two types of transistors and how to build logic gates from these transistors.
• Demonstrate basic logic gates from the corresponding CMOS gates.

2.1 Logic Gates

Basically, logic gates perform logic functions in the computer system.

Single-Input Logic Gates

The single-input logic gates take a single input and produce an output, which include a logic NOT gate and a buffer. The logic NOT gate is the most basic of all the logic gates and flips an input value. If the input A is “0” or LOW, the NOT gate produces the output “1” or HIGH. If the input A is “1” or HIGH, then it produces the output “0” or LOW, giving us the Boolean expression of: . The following figure shows the symbol and the truth table of the logic NOT gate.

Fig. 2‑1. Logic NOT gate

A buffer is a basic logic gate that passes its input, unchanged, to its output. It just repeats the input signal, giving us the Boolean expression of: . The main purpose of a buffer is to regenerate the input, usually using a strong high and a strong low. The following figure shows the symbol and the truth table of the buffer.

Fig. 2‑2. Buffer gate

Two-Input Logic Gates

For the two-input AND gate, the output Y is true only if both input A and input B are “1” or HIGH; otherwise the output Y is false, that gives us the Boolean expression of: . Note that the Boolean expression for the two-input AND gate can be written as: or just simply without the point. The following figure shows the symbol and the truth table of the two-input AND gate.

Fig. 2‑3. Two-input AND gate

For the two-input OR gate, the output Y is true or HIGH if either input A or input B is “1” or HIGH, giving us the Boolean expression of: . Note that it produces the output if only if both of inputs are “0” or LOW. The following figure shows the symbol and the truth table of the two-input OR gate.

Fig. 2‑4. Two-input OR gate

For the two-input XOR gate, the output Y is true or HIGH if either input A or input B is true, but not both, giving us the Boolean expression of: . In other words, the output Y is true if both input A and B are different. If both inputs are same, the output Y is false. The following figure shows the symbol and the truth table of the two-input XOR gate.

Fig. 2‑5. Two-input XOR gate

For the two-input NAND gate, the output Y is NOT true only if both input A and input B are “1” or HIGH; otherwise the output Y is true, that gives us the Boolean expression of: . The following figure shows the symbol and the truth table of the two-input NAND gate.

Fig. 2‑6. Two-input NAND gate

For the two-input NOR gate, the output Y is true only if both input A and input B are not true; otherwise the output Y is false, that gives us the Boolean Expression of: . The following figure shows the symbol and the truth table of the two-input NOR gate.

Fig. 2‑7. Two-input NOR gate

For a two-input XNOR gate, the output Y is true if both input A and input B are the same, either true or false, giving us the Boolean expression of: . The following figure shows the symbol and the truth table of the two-input XNOR gate.

Fig. 2‑8. Two-input XNOR gate

2.2 Noise

Anything that degrades the signal can be noise. The noise includes resister, power supply noise, coupling to neighboring wires, etc. The following figure shows how the noise affects the signal strength. There are two buffers connected serially. The output of one buffer connected to the input of the other one. Assume the output voltage of the first one is 5V. The input voltage of the second one may be 4.5 V due to the wire noise which can degrade the signal strength.

Fig. 2‑9. Noise between Driver and Receiver

In a digital circuit or system, with logically valid inputs, every circuit element must produce logically valid outputs, called static discipline. Integrated circuits use limited ranges of voltages to represent discrete values as follows:

The output characteristics:

• The logic high output ranges from V_DD to V_OH
• The logic low output ranges from V_OL to GND

The input Characteristics:

• The logic high input ranges from V_DD to V_IH
• The logic low input ranges from V_IL to GND

The voltage level difference between the logic output high (V_OH) and the logic input high (V_IH) is called the noise margin for the logic high, whereas the voltage level difference between the logic input low (V_IL) and the logic output low high (V_OL) is called the noise margin for the logic low.

In 1970’s and 1980’s, V_DD was 5V. Nowadays V_DD has dropped so we can void frying tiny transistors and save the power in the computer system. When you connect chips with different supply voltages, you should be careful; otherwise, you may burn the chip!

2.3 Transistors and Logic Gates

We can build logic gates (AND, OR, XOR, etc.) from transistors. The transistor is a 3-ported voltage-controlled switch with g: gate, d: drain, and s: source. Two ports, i.e. drain and source, can be connected depending on the voltage status of the gate. If the gate voltage is LOW (g = 0), the switch is OFF. If the gate voltage is HIGH (g = 1), the switch is ON.

Fig. 2‑10. Transistor with g = 0 and g = 1

The Metal oxide silicon (MOS) transistor has the polysilicon (used to be metal) on the gate. The oxide (silicon dioxide) insulator isolates the substrate (p-type silicon: a positively charges silicon) from the polysilicon.

As shown on the left of Fig. 2-11, if the gate voltage is low (Gate = 0), the polysilicon gate has the negative voltage and the substrate has the positive feature. There is nothing happened, meaning the source and the drain are not connected. If the gate voltage is HIGH (Gate = 1), the polysilicon gate has the positive voltage (+) and the substrate also has the positive feature. The positives push each other. It attracts the negative feature (electron: −) on the surface of the silicon dioxide insulator, which creates a channel to connect the source and the drain, meaning the source and the drain are connected.

Fig. 2‑11. Transistors: nMOS

The following figure shows the pMOS transistor. The pMOS is working in a opposite manner. If the gate voltage is LOW (Gate = 0), the switch is ON, meaning that the source and the drain are connected. If the gate voltage is HIGH (Gate = 1), the switch is OFF, meaning that the source and the drain are disconnected.

Fig. 2‑12. Transistors: pMOS

In summary, the nMOS transistor has the following features:

• If the gate voltage is LOW (Gate = 0), the switch is OFF, meaning that the source and the drain are disconnected.
• If the gate voltage is HIGH (Gate = 1), the switch is ON, meaning that the source and the drain are connected.

The pMOS transistor has the following features:

• If the gate voltage is LOW (Gate = 0), the switch is ON, meaning that the source and the drain are connected.
• If the gate voltage is HIGH (Gate = 1), the switch is OFF, meaning that the source and the drain are disconnected.

The nMOS transistor is a good component to pass 0’s, so the source port should be connected to GND. The pMOS transistor is a good component to pass 1’s, so the source port should be connected to VDD. The drain ports of both nMOS and pMOS transistors can be connected to the output port.

Fig. 2‑13. Transistor function

If the gate voltages of both nMOS and pMOS transistors are HIGH (logic “1”), the pMOS transistor is OFF and the nMOS transistor is ON. The output port has the GND voltage (logic “0”). If the gate voltages of both nMOS and pMOS transistors are LOW (logic “0”), the pMOS transistor is ON and the nMOS transistor is OFF. The output port has the V_DD voltage (logic “1”).

The NOT logic gate can be designed by connecting two transistors, nMOS and pMOS transistors, as follows:

• The logic input A connected to the gate ports of both transistors.
• The source port of the nMOS transistor connected to GND.
• The source port of the pMOS transistor connected to V_DD.
• The drain ports of both transistors connected to the output port Y.

Fig. 2‑14. CMOS Gates: NOT Gate

If the logic input A = 0, the gate voltage of nMOS transistor (N1) is LOW so that the nMOS transistor is OFF. On the other hand, the gate voltage of pMOS transistor (P1) is HIGH so that the pMOS transistor is ON. Since the pMOS transistor (P1) is ON, the logic output voltage has the V_DD voltage. That means the logic output .

If the logic input , the gate voltage of nMOS transistor (N1) is HIGH so that the nMOS transistor is ON. On the other hand, the gate voltage of pMOS transistor (P1) is LOW so that the pMOS transistor is OFF. Since the nMOS transistor (N1) is ON, the logic output voltage has the GND voltage. That means the logic output .

The NAND logic gate can be designed by connecting four transistors, where two nMOS transistors (N1, N2) are connected serially and two pMOS transistors (P1, P2) are connected parallelly, as follows:

• The logic input A connected to the gate ports of both pMOS transistor (P1) and nMOS transistor (N1).
• The logic input B connected to the gate ports of both pMOS transistor (P2) and nMOS transistor (N2).
• The source port of nMOS transistor (N1) connected to the drain port of nMOS transistor (N2).
• The source port of the nMOS transistor (N2) connected to the GND.
• The source ports of both pMOS transistors (P1, P2) connected to V_DD.
• The drain ports of both pMOS transistors (P1, P2) and the drain port of nMOS transistor (N1) connected to the output Y

Fig. 2‑15. CMOS Gates: NAND Gate

If the logic inputs and , then

• Both nMOS transistors (N1, N2) are OFF. The output port Y has no access to the GND voltage.
• Both pMOS transistors (P1, P2) are ON. The output port Y has the voltage V_DD (logic 1).

If the logic inputs and , then

• One nMOS transistor (N1) is OFF and the other nMOS transistor (N2) is ON. Two transistors connected serially, the output port Y has no access to the GND voltage.
• One pMOS transistor (P1) are ON and the other pMOS transistor (P2) is OFF. One of pMOS switches is on. The output port Y has the voltage V_DD (logic 1).

If the logic inputs and , then

• One nMOS transistor (N1) is ON and the other nMOS transistor (N2) is OFF. Two transistors connected serially, the output port Y has no access to the GND voltage.
• One pMOS transistor (P1) are OFF and the other pMOS transistor (P2) is ON. One of pMOS switches is on. The output port Y has the voltage V_DD (logic 1).

If the logic inputs and , then

• Both nMOS transistors (N1, N2) are ON. Since two transistors connected serially, the output port Y can access the GND voltage (logic 0).
• Both pMOS transistors (P1, P2) are OFF. The output port Y has no access to the voltage V_DD.

The following table summarizes the operation of all the transistors with respect to the two inputs:

How do you build a two-input AND gate?

By connecting the output port of CMOS NAND logic gate to the input port of CMOS NOT logic gate, we can design AND gate, as shown in the following figure:

Fig. 2‑16. CMOS Gates: AND Gate

The NOR logic gate can be designed by connecting four transistors, where two nMOS transistors (N1, N2) are connected parallelly and two pMOS transistors (P1, P2) are connected serially, as follows:

• The logic input A connected to the gate ports of both pMOS transistor (P1) and nMOS transistor (N1).
• The logic input B connected to the gate ports of both pMOS transistor (P2) and nMOS transistor (N2).
• The source ports of both nMOS transistors (N1, N2) connected to GND.
• The source port of the pMOS transistor (P1) connected to the VDD.
• The drain port of pMOS transistor (P1) connected to the source of pMOS transistor (P2).
• The drain port of pMOS transistor (P2) and the drain ports of both nMOS transistor (N1) and nMOS transistor (N2) connected to the output Y.

Fig. 2‑17. CMOS Gates: NOR Gate

If the logic inputs and , then

• Both nMOS transistors (N1, N2) are OFF. The output port Y has no access to the GND voltage.
• Both pMOS transistors (P1, P2) are ON. The output port Y has the voltage V_DD (logic 1).

If the logic inputs and , then

• One pMOS transistor (P1) is ON and the other pMOS transistor (P2) is OFF. Two transistors connected serially, the output port Y has no access to the V_DD voltage.
• One nMOS transistor (N1) are OFF and the other nMOS transistor (N2) is ON. One of nMOS switches is on. The output port Y has the GND voltage (logic 0).

If the logic inputs and , then

• One pMOS transistor (P1) is OFF and the other pMOS transistor (P2) is ON. Two transistors connected serially, the output port Y has no access to the V_DD voltage.
• One nMOS transistor (N1) are ON and the other nMOS transistor (N2) is OFF. One of nMOS switches is on. The output port Y has the GND voltage (logic 0).

If the logic inputs and , then

• Both pMOS transistors (P1, P2) are OFF. The output port Y has no access to the V_DD voltage.
• Both nMOS transistors (N1, N2) are ON. The output port Y has the GND voltage (logic 0).

The following table summarizes the operation of all the transistors with respect to the two inputs:

How do you build a two-input OR gate?

By connecting the output port of CMOS NOR logic gate to the input port of CMOS NOT logic gate, we can design OR gate, as shown in the following figure:

Fig. 2‑18. CMOS Gates: OR Gate